chipR
a robust chip parasitic RLC extraction software.
It is free for personal use at home.
2020.2

chipR uses Triangle to mesh the poly files exported from Klayout, and then extract one Berkeley's Spice-level netlist, which can be simulated by most circuit simulators available today.
Thank to
Klayout which is a wonderful free layout viewer and editor, a tool for the chip design engineer.
Thank to
Triangle whch is a two-dimensional quality mesh generator and delaunay triangulator.

The result matchs to other finite element method's one very well. Its advantage is that it allows desiger to extract resistance more than one port.

By now,
chipR can deal with the layout which has 3 metal layers, 2 via layers, any number of ports.
chipR can be downloaded : [chipR.exe].
example GDS file: [chipRklayout.GDS]

Klayout macro file: [chipRklayout.py]

How to use chipR:

Two Steps:
A: Use Klayout to export 4 files to Project's folder
B: Run "chipR.exe" to view meshs and extract parasitic RLC

Example: extract a GDS's parasitic R.
GDS file: chipRklayout.GDS (3 metal layers, 2 via layers)
Folder: D:\chipR
Project Name: mychip

A: Use Klayout to export 4 files to Project's folder
(1) open Klayout

(2) New Layout
(3) set layers
have 3 metal layers: 3/0, 2/0, 1/0 (can be any other number, for example, 12/0, 25/0, 98/0);
have 2 via layers: 23/0, 12/0;
have 3 port name layers: 3/1, 2/1, 1/1 (same GDS number as metal, any different datatype, for example, 12/3, 25/3, 98/3);

Note:
- metal and via's datatype must be "0";
- The GDS number of all port/name layers (for example, 3,2,1) must be same as metal's number(for example, 3,2,1). Its datatype can be any other integer (>=1);

(4) draw GDS

for example: add one port "vin" to metal 3 (GDS Number=3/0)
select layer=3/1 (the Key is metal3 port number=metal3 number, datatype=1),
draw a box(3/1) at the port location,
then add one text (3/1) "vin" which must be inside this box.

finally, we add 5 ports (vin, cdem, vref, gin, out) in this chip.
Note: VIA&Port must be rectangle.
OK.

(5) export 4 files into project folder: D:\chipR

add one python Macro:

copy all contents of "chipRKlayout.py"

then "run script from the current tab", fill all information into dialogs:
Based on the GDS layer setting, 3,23,2,12,1 are all drawing layers. The sixth number "1" is port's datatype.

Folder="D:\chipR", project name="mychip"

finally, get this:

and four new files are created into folder "D:\chipR":
All OK!

B: Run "chipR.exe" to view mesh and extract parasitic RLC
(1)
project name=D:\chipR\mychip,
means folder="D:\chipR", project name="mychip",
In folder:"D:\chipR" has 4 files:
D:\chipR\mychip.m1.poly;
D:\chipR\mychip.m2.poly;
D:\chipR\mychip.m3.poly;
D:\chipR\mychip.port.ini.

(2) Now run "chipR.exe".

(3) fill "Project Name"=D:\chipR\mychip, select the FAB's process

(4) click button "mesh" to mesh GDS file

(5) click button "R" to extract the parastic resistance
the result is a spice netlist file named "D:\chipR\mychip.1.cir" which has one line:
"Xmain vin cdem vref out gin main"
It shows that all 5 ports "vin,cdem,vref,out,gin" are be extracted.
The netlist file can be simulated by many simulators available today.

The resistance result matchs finite element method very well.

Note:
In this version, the Via's resistance is determined by the number but not by its size. So If you want get small Via resistance you must draw as many as Via. Also you can set Via's Rho very small.


Message to me:
Gurusemi's Guestbook